1. Technical Field
This disclosure relates generally to integrated circuit layouts and design, and more particularly to methods, systems, and products for generating an area efficient power switch cell of a cell library and for generating an integrated circuit layout for fabrication.
2. Description of the Related Art
In recent years, mobile devices such as smart phones and tablet computers have become increasingly sophisticated. In addition to supporting telephone calls, many mobile devices now provide access to the internet, email, text messaging, and navigation using the global positioning system (GPS). Mobile devices that support such sophisticated functionality often include many components. To remain a mobile, physical size of such components of a mobile device is a design concern. Designers of such mobile devices, often attempt to reduce the size of components or modify the components to provide greater functionality without increasing the size of the components. Such reductions or modifications may be carried out any level of the mobile device, including the layout of the integrated circuits of the components themselves.
Integrated circuit layout designers, however, are often faced with challenges that limit the amount reduction in size of components or modifications to components to increase functionality without increasing the size of the components. FIG. 1, for example, sets forth a line drawing of a birds-eye view of a prior art integrated circuit layout.
The example integrated circuit layout of FIG. 1 includes a p-type substrate 116 interleaved with parallel rows of n-wells 118. The integrated circuit layout also includes three columns of pMOS power switch cells 102. The first column includes three pMOS power switch cells 102, the second column includes two pMOS power switch cells 102, and the third column includes three power switch cells 102.
FIG. 1 also depicts an expanded view of one of the pMOS power switch cells 102 and a standard cell 108. The pMOS power switch cell 102 includes pMOS logic 110 (transistors, MOSFETs, and the like). The example pMOS power switch 102 cell includes a cell boundary 104. The cell boundary 100 equivalent (or nearly so) to double the height of the standard cell 108. The height of the standard cell 108 is equivalent (or nearly so) to the height of an n-well 118.
The pMOS power switch cell 102 is positioned with the top and bottom portion and the cell boundary 104 approximately centered in the p-type substrate 116. The pMOS power switch cell 102 is also positioned to straddle the n-well.
The standard cell 108 includes nMOS logic 112 and pMOS logic 114. The nMOS logic 112 of the standard cell 108 is positioned on the p-type substrate 116 and the pMOS logic 114 of the standard cell is position on an n-well 118.
Because the nMOS portion 112 of the standard cell ‘faces’ or, said another, is adjacent to, the pMOS logic 110 of the power switch cell 102, a spacing tolerance is required. That is, a predefined amount of space is required between the pMOS logic 110 of the power switch cell 102 and the nMOS portion 112 of the standard cell 108. Such a spacing requirement is described here as a ‘P/N spacing tolerance’ 106. In this example, the tolerance is implemented within the power switch 102 cell itself. Given a power switch cell boundary 110 of double height, the area of the internal pMOS logic 110 of the power switch cell 112 is constrained due to the required P/N spacing tolerance 106. The power switch cell, then, does not utilize the area of the cell boundary 110 efficiently.
Although the example integrated circuit layout of FIG. 1 includes a pMOS-based power switch cell 102, a p-type substrate 116, n-wells 118, and the nMOS portion 112 of the standard cell 108 facing the power switch cell 102, it is noted that the required P/N spacing tolerance is also present in other embodiments. For example, in embodiments in which the power switch cell 102 is an nMOS cell, the substrate is an n-type substrate, and the rows of wells include p-wells, a similar P/N spacing tolerance is required. In such an embodiment, the nMOS power switch is positioned with the top and bottom cell boundaries on the n-type substrate and straddling a p-well. Further, the pMOS portion 114 of the standard cell 108 faces the nMOS power switch, resulting in the required P/N spacing tolerance.
It is also noted that similar P/N spacing requirements exist when a power switch is not double height, but rather single height. In such embodiments, the single-height power switch may be positioned with the top of the cell boundary centered (or approximately centered) on a well and the bottom of the cell boundary on the substrate. When a standard cell is place below and adjacent to the power switch cell, the portion of the standard cell facing the power switch cell includes complimentary logic to that of the power switch cell. Thus, a P/N spacing tolerance is required between the two portions of complementary logic.